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This letter presents a technique for optimising CMOS based DSP systems for power. A Genetic Algorithm is used to reduce power, while tracking area and speed specifications, through the application of high level transformations. The algorithm searches for systems with the lowest power consumption within a large solution space. Results are presented which demonstrate the efficiency of the Genetic Algorithm as a power optimisation tool for complex VLSI systems. Introduction: Power dissipation has become an increasingly important parameter in the realisation of VLSI systems. It is especially important in the rapidly expanding portable computing market where the limiting factor is the operating time provided by the battery. Various techniques have been developed that tackle power reduction at different levels of the VLSI design process [1][2][3], however decisions made at higher levels will have the greatest impact on power [1]. The most significant factor affecting power consumption in a CMOS device is the product [(supply voltage) 2 × effective capacitance] [4]. This demonstrates that reduction of supply voltage will have the largest impact on power. However, research has shown that this will induce delays in the device [5]. This reduction in throughput could be compensated for with the application of a number of high level transformations [5], thus allowing supply voltage reduction while keeping throughput constant. Even with a restricted set of transformations no time efficient algorithm can be developed to determine the lowest power solution [3]. The optimisation problem is further complicated by the fact that transformations

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