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2Analog Devices, Cork, Ireland GSM & EDGE base-stations require synthesizers that can frequency hop over the full 75MHz TX or RX band in < 10us and also have very low phase noise and spurious. To date, these conflicting requirements can only be accomplished using a costly "ping-pong" architecture where one synthesizer is locking to the next desired frequency while the other is active as the LO. The proposed fast switching synthesizer can meet all these requirements with a single PLL.A common approach to reducing PLL lock time is to increase the charge pump current (I CP ) by a factor of N, while reducing the loop filter zero-resistor by sqrt(N). This increases the BW by sqrt(N) while leaving the phase margin unchanged [1]. The disadvantage of this approach is that the loop settles slowly from the phase disturbance that inevitably results when switching back to the narrow BW mode. In this paper, we describe several techniques that ensure this disturbance is no greater than the +/-5 degree limits that are acceptable for EDGE, thus allowing us to fully take advantage of the wide BW mode.• 2004 IEEE International Solid-State Circuits Conference 0-7803-8267-6/04 ©2004 IEEE

Abstr actThis paper describes a 0.35um BiCMOS process, the key aspect of which is the range of applications served by the process. To service the varied requirements, the process is designed to support high yielding, high performance active devices, high precision, well-matched passive elements, plus a variety of options such as thick metal, high-Q inductors. The process is also compatible with an existing dualvoltage CMOS process.The paper describes some novel features such as the NPN collector design, process thermal sequence and presents results from all the devices and a PLL circuit.

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