The paper presents a new method to synthesize macromodels for very large on-chip interconnection networks which can be simulated very efficiently with traditional SPICE-like simulators. The method is taking advantage of the fact that in CMOS VLSI circuits, the receiving ports of the dock distribution network can be accurately modeled by lumped passive impedances. Our method simplifies the task of simulating the interconnect by building a reduced order macromodel only for the subset of driving ports of the net. The signals at the passive ports can be determined, in a later stage, as linear combinations of a reduced set of primary signals, obtained during the simulation of the driving ports macromodel. The simulation time for the macromodels generated in this way is greatly reduced, the size of the macromodels is kept small and the accuracy is preserved.

ibis papei describes the implementation of error detection and correction logic in the optoeleetronic cache memory prototype at the tTniversitv of Pittsburgh. In this project. our goal is to Integrate a 3-f) optical meniorr directly into the iriemory liieiarcli of a personal computer. As with any optical storage system, error correction is essential to maintaining acceptable stem pert ornianee. We have implemented a I uIlv pipe lined, real time decoder for 60-hit Spectral Reed-Solomon code words. 1 he decoder is implemented in reconf igurable logic. using a single Xilinx 4000-series l'i'( per code word and is fulls scalable using multiple FPG.A' s. The current implementation operates at 33Mhz. and presses two code words in parallel per clock cycle for an aggregate data rate of 4Gb/s. 'Ne present a brief overview of the project and of Spectral ReedSolomon codes followed hr a description of our implementation and performance data.