No abstract

An off-line reconfiguration method is proposed for pipelined ADCs to improve their fabrication yield. Some nonlinearities generated by op amps in pipelined ADC stages depend on their bandwidth, while their equivalent input-referred errors depend on the stage position. From these premises, the method is conceived as a two steps process. During the first step, an alternate-test based technique determines the best stage, from the bandwidth point of view, as the front-end stage. In the second step, analog residue path interconnections and a stage scaling are configured according to the results from the first step. This method has been verified for a 10-bits ADC, designed in a 65 nm CMOS technology, by means of Monte Carlo simulations, with promising results.

This work presents an implementation of Dessouky's bootstrapped switch optimized for 65-nm CMOS technology to attain a high linearity in front-end sample-and-hold (S/H) circuits [6]. The simulations of this design show that the spuriousfree dynamic range (SFDR) achieves 100 dB for a single sinusoidal input signal of 36.36 MHz at fs=80 MHz.