This paper reports a programmable 400 μm pitch neural spike recording channel, fabricated in a 130 nm standard CMOS technology, which implements amplification, filtering, digitization, analog spike detection plus feature extraction, and self-calibration functionalities. It can operate in two different output modes: 1) signal tracking, in which the neural signal is sampled and transmitted as raw data; and 2) feature extraction, in which the spikes of the neural signal are detected and encoded by piece-wise linear curves. Additionally, the channel offers a foreground calibration procedure in which the amplification gain and the passband of the embedded filter can be self-adjusted. The amplification stage obtains a noise efficiency factor of 2.16 and an input referred noise of 2.84 μVrms over a nominal bandwidth of 167 Hz-6.9 kHz. The channel includes a reconfigurable 8-bit analog-to-digital converter combined with a 3-bit controlled programmable gain amplifier for adjusting the input signal to the full scale range of the converter. This combined block achieves an overall energy consumption per conversion of 102 fJ at 90 kS/s. The energy consumed by the circuit elements which are strictly related to the digitization process is 14.12 fJ at the same conversion rate. The complete channel consumes 2.8 μW at 1.2 V voltage supply when operated in the signal tracking mode, and 3.1 μW when the feature extraction mode is enabled.

This paper surveys the different design issues, from mathematical model to silicon, involved on the design of integrated circuits for the generation of chaotic behavior.

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