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A bst ract control constructs of a high level language (HLL) program from a This paper presents a technique for specifying change of control (e.g.branch) commands at a sequential processor's macroinstruction set level. It is shown that by representing high level language (HLL) control statements with special machine language instructions, the usual delays associated with control flow changes can be reduced.Preserving the HLL control flow information increases performance by reducing both the number of executed branches and pipeline breaks.

This paper describes techniques used by Intel's standard cell place and route system to achieve dense, high performance results. The system uses a two-step approach to achieve high performance: first reduce the average path length by producing a dense result, then adjust the result to reduce delay on the slowest paths. The performance improvement process involves interaction between the layout tool and some of Intel's performance verification tools.

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