In this paper, a fast design and implementation for sequential multiplier is presented. The suggested approach of implementation incorporates a definition of iterative addition that reduces the number of additions required in calculating the product of two binary numbers. The proposed implementation of sequential multiplier eliminates all shift operations required by conventional sequential multiplier to only one shift operation with the final accumulated result. Proposed and conventional designs of sequential multiplier are simulated in Quartus II synthesis software tool using Verilog implementation. According to the simulation results, the proposed implementation of sequential multiplier is better than conventional implementation in terms of delay time and power consumption. The proposed sequential multiplier shows an average improvement of 17.15% in delay time compared to conventional sequential multiplier.

Adders are the heart of data path circuits for any processor in digital computer and signal processing systems. Growth in technology keeps supporting efficient design of binary adders for high speed applications. In this paper, a fast and area-efficient modified carry save adder (CSA) is presented. A multiplexer based design of full adder is proposed to implement the structure of the CSA. The proposed design of full adder is employed in designing all stages of traditional CSA. By modifying the design of full adder in CSA, the complexity and area of the design can be reduced, resulting in reduced delay time. The VHDL implementations of CSA adders including (the proposed version, traditional CSA, and modified CSAs presented in literature) are simulated using Quartus II synthesis software tool with the altera FPGA EP2C5T144C6 device (Cyclone II). Simulation results of 64-bit adder designs demonstrate the average improvement of 17.75%, 1.60%, and 8.81% respectively for the worst case time, thermal power dissipation and number of FPGA logic elements.