In this paper a novel low voltage low power topology of second generation current conveyor (CCII) is presented. The internal CCII stages have been designed to obtain, at X and Z nodes, reduced parasitic impedances, so improving CCII performance. As an application example, the here proposed CCII, designed in standard CMOS technology (AMS 0.35 µm), has been used to design an integrated resistive sensor interface, showing the capability of compensating the non idealities of passive and active components. Preliminary and post-layout simulations show an excellent linearity for what concerns sensor sensitivity.

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