Multiprocessor system on chip (SoC) contains hundreds of cores on a chip that require high speed interconnections for fast data communication between the cores. With an increased number of cores, an on-chip bus or a multilayer bus architecture is the bottleneck for SoC. In contrast, Network-on-chip (NoC) mitigates the flaws of the SoC technology by introducing high scalability, improved communication performance and lesser power consumption. It provides such an on-chip communication architecture that allows multiple cores to communicate via packets routed on a network. A Network-onSystem (NoS) architectural framework caters for the major issues of high latency and decreased throughput of reprogrammable and reconfigurable hybrid embedded systems. This paper presents a novel idea of hybrid processors configuration in NoS using an Integrated Development Environment (IDE) generated middleware. The user will be able to configure or reconfigure the NoS, whereas the intercommunication of hybrid processors on the NoS will take place in an abstraction layer without any user intervention. The basic model of NoS and the proposed prototype for GUI based IDE used for middleware generation have been explained in detail. The paper also discusses how such an IDE can be used in the middleware generation of real-time applications like SDR. The proposed methodology is ideally suited to address the complexities of a hybrid embedded system.