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In this paper, we proposed a novel heuristic method based on Imperialist competitive Algorithm (ICA) to design combinational logic modules which performing different arithmetic functions. According to conventional methods, for multi functional circuit, a distinct circuit is designed for each specific function and then all of them are combined together with multiplexer(s) to have desired circuit. But in our proposed method the whole circuit structure is designed and optimized in one procedure by ICA Algorithm. We tried to optimize the area of circuit by reducing the number of transistors forming logic gates. Simulation results show that our method significantly reduces the number of transistors and gates and accordingly the circuit area.

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