In this paper, a new data reading technique for a bus of lines is proposed for fast operation. The proposed method utilizes multiple reference voltages available within a line's receiving logic and the initial conditions of wires in order to determine early and accurately the transmitted data of the current cycle. The presented technique does not require repeater insertion for reasonably long lines and it can significantly accelerate signal propagation. Experimental results are given in the 65 nm CMOS process for interconnects of various lengths.

Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation underestimates the number of sensitizable paths per circuit. This leads to inconclusive and overly optimistic results when a worst-case analysis is required. In this paper, we present a zero-suppressed binary decision diagram (ZBDD) centered framework, for a complete consideration of all potentially sensitizable paths per circuit. The proposed method is validated in logic paths by evaluating worst-case transient-wave electrical characteristics, such as maximum duration and corresponding amplitude at the circuit outputs.

Coupling and increasing wire resistance on interconnect fabrics undermine the speed of the transient electrical signals. A brute-force approach for a crosstalk-reduced design relies on increasing the distance of interconnects from each other and using additional repeated logic. A pipelined bus-architecture exploiting the existing electrical noise is proposed. Process variations are taken into consideration in the analysis. The proposed technique is validated for the 65nm and 90nm CMOS processes for interconnects of various lengths.9th International Symposium on Quality Electronic Design 0-7695-3117-2/08 $25.00

Random voltage changes on bus lines may lead to reading corrupted digital data. A novel methodology for detecting such anomalies is proposed. It uses multiple threshold voltages at the receiver-end. In our earlier work we have shown that multiple voltage thresholds improve the performance along buses, especially when they are coupled as is often the case in deepsubmicron. This work shows that multiple thresholds can also be used to identify voltage perturbations on-line. The mechanism is presented assuming that each line can have only one aggressor. The efficiency of the methodology is evaluated for perturbations in single and multiple receiving nodes of a data bus.

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