In this paper, we propose a hardware architecture of high-speed sorted QR decomposition for a 4x4 MMSE MIMO decoder. A QR decomposition (QRD) is commonly used in many MIMO detection algorithms. In particular, a sorted QR decomposition (SQRD) is a advanced algorithm to improve a MIMO detection performance. The proposed architecture can decompose an augmented channel matrix for MMSE detection by using modified Gram-Schmidt algorithm with pipelining and resource sharing processing. This architecture can be applied in a high-throughput MIMO-OFDM system such as IEEES02.11n which supports data throughput of up to 600Mbps. We imple ment the proposed architecture with 334k gates in 90nm CMOS technology. The proposed design can achieve a high performance of up to 50.0 million 4x4 SQRD operations per second with the maximum operating frequency of 300 MHz.

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