Abstract

In this paper, green Image ALU is designed in Xilinx ISE 14.6 using LVDCI(Low Voltage Digitally Control Impedance) and LVDCI_DV2(Half Impedance Version of LVDCI) I/O standard in 40nm Virtex-6 FPGA. By using LVDCI technology we achieve energy efficiency with respect to low voltage impedance. In this whole work, we are using three different classes of LVDCI and LVDCI_DV2 and observe that when image ALU operates at 1THz device operating frequency with LVDCI_15 and LVDCI_DV2_15 I/O Standard, there is 52.87% and 65.67% reduction in IO power than LVDCI_25 and LVDCI_DV2_25 Standard respectively. In Image ALU, there are 16 different operations (logical and arithmetic). There is no any change in Clock power, Leakage power and Signal power of Image ALU using LVDCI and LVDCI_DV2 I/O Standard.

In this paper an approach called Capacitance Scaling Ambient Temperature (CSAT) is used to design an energy efficient as well as thermal efficient GCD generator. Energy efficient means it dissipates less power either IO power or leakage power than their traditional counterpart. Thermal efficient means junction temperature of FPGA is lesser than their traditional counterpart. Where, Junction temperature is the highest temperature of an actual device or silicon die in FPGA. Our work shows the variance of I/O power and Junction temperature at different capacitance values under different frequencies. There is 15.22% reduction in I/O Power when we scale down capacitance from 100pF to 80pF. There is 29.31%, 44.83%, 58.62%, and 74.14% reduction when we further scale down capacitance to 60pF, 40pF, 20pF and 0pF. When we scale down capacitance from 100pF to 80pF, 60pF, 40pF, 20pF and 0pF, there is 3%, 6%, 9.14%, 12.14% and 15.19% reduction in junction temperature respectively at 100GHz device operating frequency. Virtex-6 is our target FPGA device for this design.

and is more in the case of 28nm . Changing the parameter (Temperature) doesn't affect the clock power in both cases (Gated and Non-gated).

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