A comparator plays a significant role in the developing of ADC. This comparator aims to get small offset value for high resolution. Several architectures present to optimize the offset voltage. The comparator designed for a 14-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). The main advantage of the implemented comparator of SAR ADC, which is the right choice for high resolution. This schematic design and layout simulation have implemented in Silterra C18G process 0.18um CMOS Technology by using Synopsys EDA Tools with transient and Monte Carlo. A double tail regenerative comparator is studied and investigated during this project. The simulation results complete with a 3.3V power supply. This comparator operates in 5MHz clock frequency with offset voltage for the latch is 32mV.

Digital to Analog Converter (DAC) is the essential block to convert an input digital signal into analog signal. The switching technique is the important parameter that will affect the performance of DAC where to ensure the analog output signal can be obtained without any missing code. The capacitor DAC is most famous architecture used to design the DAC and it produce high power efficiency. But, the number of unit capacitors in DAC increase exponentially due to the increasing of resolution and a DAC block occupies a largest area among many internal blocks in Successive Approximation Register (SAR) Analog to Digital Converter (ADC). The DAC was designed for 14-bit SAr ADC using a hybrid Rc DAC architecture. The design of DAC has been carried out by using 0.18μm CMOS Silterra process Technology. The simulation results are done with 3.3V voltage supply and obtained DNL within -0.39 LSB to 0.238 LSB. It occupies an area of 0.614μm2.