An efficient k-Winners-Take-All (kWTA) module that selects and sorts the k largest data from multiple binary data is presented in this paper. This module is implemented by pipelining a k largest element selector and a sorting circuit, both of which operate in the bit-serial method. The module completes finding and sorting the k-largest data from N of m-bit binary data in m clock cycles. This could be used as a hardware module for the ASIC design which can be employed for any ASIC chip requiring kWTA operation of digital data. The time complexity of this module is O(N) and its delay is independent of the k value. The overall kWTA operation is completed in m cycles with an internal clock which is adjusted to the number of data. According to the simulation results, the required clock cycle time (Tclk) is 68.4 ns for 1024 of 10-bit binary numbers so that the module finishes the operation by 684 ns. Keywords—Winner-Take-All, k-Winners-Take-All circuit, Digital kWTA circuit, kWTA architecture, kWTA module.