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This paper presents the design of low complexity LDPC codes decoders for the upcoming WiFi (IEEE 802.11n

The principle of "layered decoding" is extended to those codes not especially conceived for this practice, as to benefit of the increased convergence speed. Two different strategies are considered to solve the problem and the related architectures presented: one more straightforward, and based on the use for the soft output of the last value originated in a layer; the other based on the computation of the variation (or delta) of the soft output metrics to allow concurrent updates. Then, as in architecture-first approach, the performance are assessed for several widths of the layer, which remarks the robustness of the delta-mechanism to high parallelisation factors. As in the exact layered decoding, the average boost of two times in the convergence speed is shown.

Despite recent advances in the microelectronics technology, the implementation of high-throughput decoders for LDPC codes remains a challenging task. This paper aims at summarising the top-down design flow of a decoder for a structured LDPC code compliant with the WWiSE proposal for WLAN. Starting from the system performance analysis with finite-precision arithmetic, a high-throughput architecture is presented as an enhancement of the state-of-the-art solutions, and its VLSI design detailed. The envisaged architecture is also very flexible as it supports several code rates with no significant hardware overhead. The overall decoder, synthesised on 0.18 µm standard cells CMOS technology, showed remarkable performances: small implementation loss (0.2 dB down to BER = 10 −8 ), low latency (less than 6.0 µs), high useful throughput (up to 940 Mbps) and low complexity (about 375 Kgates). Proceedings of the 2005 8th Euromicro conference on Digital System Design (DSD'05) 0-7695-2433-8/05 $20.00 © 2005 IEEE Proceedings of the 2005 8th Euromicro conference on Digital System Design (DSD'05) 0-7695-2433-8/05 $20.00 © 2005 IEEE

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