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This thesis presents a test architecture for reducing the cost of testing an integrated circuit (IC). The cost of testing an IC is based on the volume of test data that needs to be loaded during the testing process and the time required to test the circuit. The proposed solution reduces both these factors using a new architecture to load test.data in parallel. Typically, test data is loaded into a circuit using chains of internal storage elements, called scan chains and each of these chains is connected to the inputs of the circuit under test. When loading the test data in parallel, many scan chains share the same input. The scan chains that share the same input must contain the same data, creating constraints on the test data that can be loaded. The constraints introduced increase as the number of chains that are loaded in parallel increases. Therefore, certain defects in a circuit might not be testable, if a large number of chains are loaded in parallel. The proposed architecture reduces the constraints of parallel loading by changing the inputs that drive each scan chain during the testing process. We call this change, reconfiguration of the scan chains. This thesis presents two methods of determining how to reconfigure the scan chains. The first method provides the largest gains, but requires a large amount of additional computation when creating the test data. Therefore, a second method that is less effective, but requires no additional computation is also presented. Experimental results show as much as a factor of 170 reductions in both the test time and test data volume relative to the standard serial testing.

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