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This paper describes a high-performance low V MIN SRAM with a disturb-free 8T cell. The SRAM utilizes single-ended buffer Read, and cross-point data-aware Write Word-Line structure with adaptive VVSS control to eliminate Read disturb and Half-Select disturb, thus facilitating bitinterleaving architecture and achieving low V MIN . A 512Kb test chip is implemented in UMC 55nm Standard Performance (SP) CMOS technology. The measurement results demonstrate operating frequency of 943MHz at 1.2V VDD and 209MHz at 0.6V VDD. I. INTRODUCTIONAs more memories are integrated on a chip, reducing the SRAM power has become an important issue. Lowering SRAM supply voltage is the most effective technique to reduce SRAM active power and leakage power. However, PVT variations and the resulting degradation of SRAM Static Noise Margin (SNM) and Write-ability become more severe with technology and supply scaling. These constraints limit scaling of SRAM cell area and supply voltage. To improve SRAM stability, Write-ability, and V MIN , various cells and techniques have been proposed, such as 8T cell [1], cross-point 8T cell [2], cross-selected 10T cell [3], column-decoupled 8T cell [4,5], and transient negative BL Write-assist [6].In this paper, we present an 8T SRAM featuring Read stack buffer, cross-point dataaware Write Word-Line structure and adaptive VVSS control to realize a disturb-free cell to facilitate bit-interleaving architecture and low V MIN design target. Dual V TH cell and self-triggered variation-tolerant negative BL Write-assist are employed to improve Read/Write performance.