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We present a comprehensive overview of a design methodology and environment that we developed to enable the implementation of microprocessors and other complex logic circuits using the adiabatic quantum-flux-parametron (AQFP) superconductor logic family. The design environment is catered for both the AIST 10 kA cm −2 Nb high-speed standard process as well as the AIST 2.5 kA cm −2 Nb standard process (STP2). We detail each aspect of the design flow, highlighting improvements in cell design, and new developments in circuit retiming to reduce the number of synchronizing buffers in the circuit datapath. With retiming, we expect a 14-37% reduction in the overall Josephson junction (JJ) count for some benchmarks. Finally, we show the successful experimental demonstration of an arithmetic logic unit and data shifter for an AQFP microprocessor using the established methodology and environment. The demonstrated circuits show full functionality and wide excitation current margins of nearly ±30%, which corresponds well with simulation results.

Adiabatic Quantum-Flux-Parametron (AQFP) logic is an adiabatic superconductor logic family that has been proposed as a future technology towards building extremely energy-efficient computing systems. In AQFP logic, dynamic energy dissipation can be drastically reduced due to the adiabatic switching operations using AC excitation currents, which serve as both clock signals and power supplies. As a result, AQFP could overcome the power/energy dissipation limitation in conventional superconductor logic families such as rapid-single-flux-quantum (RSFQ). Simulation and experimental results show that AQFP logic can achieve an energy-delay-product (EDP) near quantum limit using practical circuit parameters and available fabrication processes. To shed some light on the design automation and guidelines of AQFP circuits, in this paper we present an automatic synthesis framework for AQFP and perform synthesis on 18 circuits, including 11 ISCAS-85 circuit benchmarks, 6 deep-learning accelerator components, and a 32-bit RISC-V ALU, based on our developed standard cell library of AQFP technology. Synthesis results demonstrate the significant advantage of AQFP technology. We forecast 9,313×, 25,242× and 48,466× energy-per-operation advantage, compared to the synthesis results of TSMC (Taiwan Semiconductor Manufacturing Company) 12 nm fin field-effect transistor (FinFET), 28 nm and 40 nm complementary metal-oxide-semiconductor (CMOS) technology nodes, respectively.

The Adiabatic Quantum-Flux-Parametron (AQFP) superconducting technology has been recently developed, which achieves the highest energy efficiency among superconducting logic families, potentially 10 4 -10 5 gain compared with state-of-theart CMOS. In 2016, the successful fabrication and testing of AQFP-based circuits with the scale of 83,000 JJs have demonstrated the scalability and potential of implementing largescale systems using AQFP. As a result, it will be promising for AQFP in high-performance computing and deep space applications, with Deep Neural Network (DNN) inference acceleration as an important example.Besides ultra-high energy efficiency, AQFP exhibits two unique characteristics: the deep pipelining nature since each AQFP logic gate is connected with an AC clock signal, which in AQFP, (ii) a high-accuracy sub-sampling (pooling) block in AQFP, and (iii) majority synthesis for further performance improvement and automatic buffer/splitter insertion for requirement of AQFP circuits. Experimental results suggest that the proposed SC-based DNN using AQFP can achieve up to 6.8 × 10 4 times higher energy efficiency compared to CMOS-based implementation while maintaining 96% accuracy on the MNIST dataset.