In the present era of high speed communication, wireless technology plays a predominant role in data transmission. In the timeline of wireless domain, Wi-Fi, Bluetooth, ZigBee are some of the standards used in today's wireless medium. In addition, WiMax is introduced by IEEE as IEEE 802.16 standard for long distance communication, and mobile WiMax as 802.16e. WiMax is an acronym of worldwide interoperability for microwave access. It helps to provide wireless transmission with high quality of service in a secured environment. Privacy across the network and access control is the predominant goal in the wireless protocol. In the wireless environment one of the most widely used security algorithms in MAC layer is Advanced Encryption Standard (AES). Especially Medium Access Control (MAC) sub layer should be evaluated in the security architecture. AES is used in the MAC layer that consumes more power and involves high cost. So, in this paper an optimized architecture of AES 128 bit counter mode security algorithm for MAC layer of 802.16e standard is proposed. The SBOX and MixColumn transformation are modified in the architecture of AES to achieve optimized power and delay. The design has been implemented in Xilinx virtex5 device and power has been analyzed using XPower analyzer. It is compared with two standard existing architectures. The simulation results revealed a power reduction of 41% compared to existing one.

Purpose The growing trends in the usage of hand held devices necessitate the need to design them with low power consumption and less area design. Besides, information security is gaining enormous importance in information transmission and data storage technology. In addition, today’s technology world is connected, communicated and controlled via the Internet of Things (IoT). In many applications, the most standard and widely used cryptography algorithm for providing security is Advanced Encryption Standard (AES). This paper aims to design an efficient model of AES cryptography for low power and less area. Design/methodology/approach First, the main issues related to less area and low power consumption in the AES encryption core are addressed. To implement optimized AES core, the authors proposed optimized multiplicative inverse, affine transforms and Xtime multipliers functions, which are the core function of AES’s core. In addition, to achieve the high throughput, it uses the multistage pipeline and resource reuse architectures for SBox and Mixcolumn of AES. Findings The results of optimized AES architecture have revealed that the multistage pipe line and resource sharing are optimal design model in Field Programmable Gate Array (FPGA) implementation. It could provide high security with low power and area for IoT and wireless sensors networks. Originality/value This proposed optimized modified architecture has been implemented in FPGA to calculate the power, area and delay parameters. This multistage pipeline and resource sharing have promised to minimize the area and power.

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Health monitoring of human being can be done using implant or wearable sensors. Making use of these sensors to form a network are aptly called as Wireless Body Area Sensor Networks (WBASN). Better performance and energy saving can be accomplished in a challenging way in this type of network. National Rural Employment Guarantee Act in India provides employment for people in rural areas. This involves more intense physical work in the open environment. People involved in this work tend to feel fatigue if they work for prolonged duration. We have conducted experiments in several scenarios to determine the stamina level of employed people and proposed ways to provide how man power can be efficiently improved by giving optimal break time and energy supplement drinks to improve the stamina level. Moreover energy of sensors may be efficiently improved by compressing the data before transmitting them to servers by suitable algorithm as discussed in our paper.