An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD, and TEM analysis. Dedicated characterization techniques for such bonding are presented.Bonding of metal surfaces is extensively used for MEMS sealing, power devices, heat dissipation or 3D interconnections. For these applications, techniques such as thermo compression, with or without eutectic alloys or adhesives layers, bumps with low temperature solders or direct bonding are extensively implemented techniques. 1-7 Moreover, for More Moore and More than Moore applications, low temperature bonding and metal bonding are becoming the main drivers of the latest developments. As copper is the main metal used for CMOS interconnects, a high-density Cu interconnection between layer structures, is expected for future three-dimensional integration of electronic devices fabricated on the basis of different technology/ design concepts. In this paper, an overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD and TEM analysis. Dedicated characterization techniques for such bonding are presented. Hybridization Techniques ReviewCopper is the most (compared to other possible bonding metals) promising candidate for 3D integration technology either for TSV filling or interstata hybridizing. The main reasons of this choice is the widely use of copper in semiconductor device industries and the cost of ownership. On the other hand, the choice of the metal bonding technique is still an open question. Bonding anneal temperature, duration of the annealing, need of an underfill, size and pitch of the interconnect pads, availability of the technique for wafer bonding or die bonding are key parameters of the final choice. The main studied bonding techniques can be divided into two groups: with and without thermal compression.Bonding with a compression force: Diffusion bonding.-The thermal compression bonding is a well known technique. 8-10 Wafers or dies are pressed together with a controlled force in a bonding tool, while heating is applied (400 C) to allow the bonding diffusion mechanism. Thanks to the compression force, the surfaces roughness is not a limiting factor as the surface asperities are deformed at the bonding interface, therefore surfaces with a roughness in the range of 5 nm can be used. Copper oxide should be avoided or removed right before ...

Three-dimensional ͑3D͒ technology is the next step in the development of microelectronic devices. Vertical interconnection is one of the challenging issues. Metal bonding might be one of the possible techniques to address it. In this work, direct Cu/Cu bonding at room temperature, atmospheric pressure, and ambient air was investigated. At room temperature, a 2.8 J/m 2 bonding toughness was achieved. An electron energy loss spectroscopy spectrum pointed out the absence of copper oxide at the interface. Morphological evolutions vs postbonding annealing were presented with transmission electron microscopy and X-ray diffraction analyses. The ohmic behavior of the bonding was highlighted.