Today many design houses must outsource their design fabrication to a third party which is often an overseas foundry. Split-fabrication is proposed for combining the FEOL capabilities of an advanced but untrusted foundry with the BEOL capabilities of a trusted foundry. Hardware security in this business model relates directly to the front-end foundry's ability to interpret the partial circuit design it receives in order to reverse engineer or insert malicious circuits. The published experimental results indicate that a relatively large percentage of the split nets can be correctly guessed and there is no easy way of detecting the possibly inserted Trojans. In this paper, we propose a secure split-fabrication design methodology for the Vertical Slit Field Effect Transistor (VeSFET) based integrated circuits. We take advantage of the VeSFET's unique and powerful two-side accessibility and monolithic 3D integration capability. In our approach the design is manufactured by two independent foundries, both of which can be untrusted. We propose the design partition and piracy prevention, hardware Trojan insertion prevention, and Trojan detection methods. In the 3D designs, some transistors are physically hidden from the frontend foundry_1's view, which causes that it is impossible for this foundry to reconstruct the circuit. We designed 10 MCNC benchmark circuits using the proposed flow and executed an attack by an in-house developed proximity attacker. With 5% nets manufactured by the back-end foundry_2, the average percentage of the correctly reconstructed partitioned nets is less than 1%. CCS Concepts • Security and privacy~Hardware security implementation • Security and privacy~Tamper-proof and tamper-resistant designs • Security and privacy~Hardware attacks and countermeasures • Hardware~Integrated circuits • Hardware~3D integrated circuits • Hardware~Emerging architectures

This study implements the metal-oxide-semiconductor (MOS) type gas sensor using the TSMC 0.35 μm 2P4M process. The gas concentration is detected based on the resistance change measured by the proposed sensor. This design has three merits: (1) low-cost post-CMOS process using metal/oxide wet etching, (2) composite sensing material based on ZnO-SnO2 coating on the CMOS-MEMS structure, (3) vertical integration of heater and ZnO-SnO2 gas-sensing films using CMOS-MEMS and drop casting technologies. Proposed design significantly increase the sensitivity at the high operating temperature. In summary, the sensitivity of presented sensor increased from 0.04%/% (O2/N2) at near room operating temperature to 0.2%/%(O2/N2) at near 140 °C for the range of 5–50% oxygen concentration.

This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration-friendly vertical terminals and horizontal channel manufactured based on SOI wafer with conventional CMOS fabrication hardware. The second gate provides the capability of transistor behavior adjustment and the potential for advanced circuit designs. The results show that VeSFET can provide high I eff to I off ratio, low gate capacitance, high V t /V g2s , and competitive drive capability with respect to a reference FinFET of comparable dimensions.

This paper describes an on-chip intellectual property (IP) testing platform, Universal High Frequency Test structure (UHFTs), which makes logic, memory, and analog / mixed-signal IPs at-speed testable in the same testing structure. Any functional testing pattern can be loaded from an external pattern generator or a tester through standard 5-pin JTAG interfaces operating at 10MHz or below. The on-chip multichannel JTAG interface and elastic buffers convert an externally supplied pattern to an on-chip at-speed high-frequency pattern. The pattern can have address, data, and control fields. Each field is applied as input to a DUT in any one of 16 available DUT sites, fully synchronized to the on-chip global clock. The output from the DUT is captured at-speed and stored in an output buffer. The content of the output buffer is read out to an external tester through the elastic-buffer and JTAG interfaces under a program control. UHFTs, implemented in TSMC 28-nm High Performance CMOS process, has been successfully used in digital, including ATPG, BIST, and vector-based tests with the capability of mixed-signal and analog tests. UHFTs have been designed with a frequency goal of 4 GHz in TSMC 28-nm CMOS process in the slow corner.

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