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The paper presents a prototype integrated circuit built in a 40 nm CMOS process for readout of a hybrid pixel detector. The core of the IC constitutes a matrix of pixels with the pixel size of m m. The paper explains the functionality and the architecture of the IC, which is designed to operate in both the standard single photon counting mode and the single photon counting mode with interpixel communication to mitigate negative effects of charge sharing. This article focuses on the measurement results of the IC operating in the standard single photon counting mode. The measured ENC is rms (for the peaking time of 48 ns), the gain is V , while the effective threshold dispersion is rms.

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