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In this paper, we propose a VLSI implementation scheme for region split and merge image segmentation. Region splitting is done using a parallel pixel network. We propose a modified merging criterion to reduce the execution time and corresponding hardware implementation is also proposed. We have shown the modified merge criterion will reduce the number of merging iteration steps. Implementation results are encouraging as the processing time in hardware with a 100MHz clock in XILINX VIRTEX IV FPGA is achieved a few order lower than the software implementation.

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