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Quantum Dot Cellular Automata is one of the six emerging technology which can overcome the limitations of current transistor based technology. Quantum Dot Cellular Automata is popular technology due to its extremely small feature size and ultra low power consumption. In this paper new XOR gate using Coupled Majority Voter Minority gate is proposed. Using this proposed XOR gate Binary to Gray Code and Gray to Binary Code Converters are designed. This paper shows the performance analysis of Proposed XOR circuit and it has been proved that XOR gate and Binary to Gray and Gray to Binary Code converters are efficient in terms of area, complexity, latency and wire crossings. QCADesigner 2.0.3 tool is used for design and simulation of these circuits. Keywords-Coupled Majority Voter Minority (CMVMIN), Quantum Dot Cellular automata (QCA), Binary to Gray Code Converter, Gray to Binary Code Converter, Majority Voter (MV).I.

This paper presents implementation of S-Box for Advanced Encryption Standard (AES) algorithm. The proposed design structure is implemented in verilog. Previous works rely on lookup tables to implement the S-Box of AES algorithm which incurred a fixed and unbreakable delay. The proposed design employs combinational logic based composite field arithmetic AES S-Box which results in optimized area in terms of FPGA slices compared to ROM based lookup table. The proposed 4stage pipelined implementation of S-Box is carried on the XC3S100E device of Xilinx FPGA with verilog code which requires 34 slices and 67 4-input LUTs and also maximum clock frequency of 187.071 MHz.

In this paper, we present a low complexity Quasi-cyclic -low-density-parity-check (QC-LDPC)