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AbstTact-Two dimensional, separable signal models a r e proposed for modeling t h e effects of inter-symbol a n d inter-track interference in high-density rnagnetic storage media. T h e optimum (minimum mean-squared error) linear a n d decision feedback equalizers based on t h e s e models a r e developed.T h e use of a two dimensional LMS algorithm for adaptive updating of t h e equalizer coefficients is discussed a n d analytical results presented. Finally, simulation evidence is provided t o predict t h e performance improvements achievable based on t h e s e models vis-a-vis o n e dimensional equalization. P a p e r approved by t h e Editor for Transmission Systems of t h e I E E E Communications Society. Manuscript received November 15, 1991; revised J u n e 15, 1992, February 15, 1993. This work was supported by d NSF under NCR89-14431 a.n d P. S. Kumar is with 'WINLAB, Rutgers University, Piscataway, N J 1-;, n = o , 72 = 1, ( 2 ) 0 tl1er \I1 k l ' . 08855. Pennsylvania, Philadelphia, PA 19104. S. Roy is with t h e Department of Electrical Engineering, University of IEEE Log Number 9400921. 0090-6778/94$04.00 0 1994 IEEE from the University of Califoinia, all in Electrical Eugineering in 1985 and 1988 respectively, as well as an M. .4. in Statistics and Applied Only the 'Onstant terms in the expansion remain and we get Probability in 1958. Since 19S5, he has been an Assistant Professor at the Moore School of Electrical Engiueeliiig, University of Pennsylvania. His research interests span the mea3 of signal processing, communication theory nnrl performance evaluatiou of cornmunicat ion systems.

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The Residue number system (RNS) has been employed for efficient parallel carry-free arithmetic computations in DSP applications. Residue addition is the instrumental component in implementing residue converters and channels in RNS. On the other side Reversible Logic is becoming one of the potential power optimization techniques in Low Power CMOS design. In this research paper we have proposed CMOS implementation of two different reversible logic architectures for 4-bit generic