Now days in area of computer science Green computing is creating revolution by bringing some new digital component with less power consumption. Our research work is created on this idea. In this paper our objective is to come up with High Performance ALU design for IOT based processor by reducing the power consumption. For calculating total power consumption of FPGA based ALU we used five different voltage (0.95,1.0,1.05,1.10,1.15,1.20) and calculated IOs, Leakage power at four different IOs standard (SSTL18_II, SSTL15, SSTL135, SSTL15_R). In experiment we found the best result with SSTL15_R IO standard. We think that the application of this design will definitely help to design in futuristic IOT based processor development.

This chapter will cover the basic problems of women in South Asian countries. For this, a group survey is taken in India, Sri Lanka, Singapore, Malaysia, Thailand, Myanmar, and Nepal covering around 200 women about their basic problems in personal and professional lives and lifestyle and house management routine activities. The chapter will cover the basic segment of artificial intelligence and its support in maintaining the health parametric card for the household makers. The chapter will also assist the women in the kitchen with the help of artificial intelligence, especially in cooking and digital health menu selection. A special segment in the chapter will also address the cleanliness of the house with the help of A.I.-supporting tools and gadgets. Last but not the least, the chapter will also address the security of the household makers especially in day hours when they are alone in the houses. The chapter will be an innovative research to understand the better half of the society and to address their day-to-day problems with technological interventions.

Objectives: The 4-bit ALU of a RISC processor is designed as shown by the researcher in this paper. The 4-bit ALU used in this work can perform 24 = 16 various arithmetic and logical operations, including addition, subtraction, multiplication, and division as well as logical AND, OR, NAND, NOR, NOT, XOR, XNOR, INCREMENT, DECREMENT, ROTATE LEFT, and ROTATE RIGHT. Methods: The author used the Vivado simulation tools with the Verilog HDL language to build the FPGA-based ALU, and the SP701 Spartan FPGA board was used to implement the entire design. It has been implemented to use energy-efficient IO standard approaches. Findings: By calculating the overall power usage at the pre- and post-levels, this research has developed a new method for building energy-efficient FPGA-based ALUs. Author utilized Vivado simulation tool for this investigation. The SP701 FPGA board has also been used to implement this idea. Novelty: The Internet of Things and other emerging digital era technologies will undoubtedly benefit from this research work, and its energy efficient design will support environmental initiatives.