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As the next generation standard of video coding, the High Efficiency Video Coding (HEVC) aims to provide significantly improved compression performance in comparison with all existing video coding standards. We propose a fourstage pipeline hardware architecture on a quarter-LCU basis of deblocking filter in HEVC. Coupled with the novel filter order, a memory interlacing technique is adopted to increase the throughput, which can access the data in the process of both vertical and horizontal filtering efficiently. As a result, our design can support 4Kx2K (4096x2048) at 30 fps applications with merely 28MHz working frequency.

To meet the requirements of scientific research personnel on wide range and high-precision variable inductor. The new digital inductor is based on the impedance converting circuit. The new active impedance converting circuit is formed by integration operational amplifiers, a small amount of resistance and capacitance. Through control of the switching circuit part line, thus producing the equivalent pure inductance. Experimental results show that using digital potentiometer and analog switches adjust circuit resistance to adjust the inductance value. So that digital equivalent inductance has certain advantages in the circuit experiment debugging and inductance adjustable electronic products.

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