This paper describes the implementation of a system based on Pulse Coupled Neural Networks (PCNNs) and Field Programmable Gate Arrays (FPGAs). The PCNN implemented is oriented to the industrial application of segmentation in sequences of images. The work went through several real physical stages of implementation and optimization to achieve the needed performance. The greatest performance achieved by the digital system was of 250M pixels per second, enough to process a sequence of images in real time. Details of these stages about the neuron implementation with different Altera's FPGAs families are presented. Furthermore, the implementation is compared with previous implemented schemes based on floating point DSP microprocessor.

This paper describes the implementation of a system based on Pulse Coupled Neural Networks (PCNNs) and Field Programmable Gate Arrays (FPGAs). The PCNN implemented is oriented to the industrial application of segmentation in sequences of images. The work went through several real physical stages of implementation and optimization to achieve the needed performance. The greatest performance achieved by the digital system was of 250M pixels per second, enough to process a sequence of images in real time. Details of these stages about the neuron implementation with different Altera's FPGAs families are presented. Furthermore, the implementation is compared with previous implemented schemes based on floating point DSP microprocessor.