90 • phase shifters are used in various communication applications such as analytic signal (I and Q) generation, image rejection and Single Side Band (SSB) modulation. In this article, we present an efficient VLSI architecture for the generation of IQ signal with reduced amplitude and phase mismatches using phase-orthogonal FIR phase shifter. The proposed design and implementation reduces the constant multipliers in FIR filter from 2N to N /2 in two steps. In the first step, the filter passband is centered around 0.25fs which makes the alternate filter coefficients zero, reducing the multiplier count to N. In the second step, the hardware architecture is designed in such a way that the time-reversal property of the two filters is exploited to reduce further the multiplier count to N /2. A transposed FIR filter structure with Canonic Signed Digit(CSD) coefficients is adopted for implementation on FPGA. The dual filter approach and the optimization technique has resulted in better filter performance compared to the conventional Hilbert filter approach. The FPGA implementation gives a phase and amplitude ratio error of −0.17 • and 0.0002 dB for a filter order of 26 and −0.21 • and 0.0053 dB for a filter order of 32 respectively. Despite having two filters, the area increase is only 50% of widely used Hilbert transformer method that uses a single FIR filter. The designed phase shifter shifter is used to simulate an SSB modulator. A side band suppression of 18.9dB is achieved with the proposed phase-orthogonal phase shifter, which is ≈8 dB better than the Hilbert filter based SSB modulator.