With a growth of E-commerce and availability of resources over internet number of attacks on servers providing these services, resources are also increased. Denial of service and Distributed Denial of Service are most widely launched attacks against these servers for preventing legitimate users from accessing these services. This paper presents architecture of offline Signature based Network Intrusion Detection System for detection of Denial/Distributed Denial of Service attacks against HTTP servers using distributed processing and Naïve Bayesian classifier. Experimental results are provided to prove the efficiency of proposed architecture.

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This work reports Partial Reconfiguration (PR) by which selected areas of an FPGA can be reconfigured during runtime. Today cryptographic algorithms are not safe also embedded cryptographic hardware is costly. Hence to make it cost effective and to provide more secureness reconfigurable hardware such as FPGA is used with the concept of partial reconfiguration. This work gives briefings about the method of hardware implementation for AES encryption algorithm with Dynamic reconfigurable keys. Our implementation reaches very good efficiencies than the compared one as we have adopted our own methodology for key expansion. With the combination of adopted methodology & used FPGA this paper shows better agreement as compared to previous work. This implementation could be a good solution to preserve confidentiality and convenience to the information in the numeric communication.

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