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Graph-based methodologies for supergate design have gained relevance recently. Due to the non-series-parallel arrangements and the transistor sharing technique, these methodologies can deliver a network with fewer transistors, leading to an efficient logic design. However, through its optimization processes, these methods introduces some topology particularities in the logic network, which impacts directly in the layout. This paper presents a methodology to identify these aspects in order to guide the cell layout generation. The results were performed over a set of intensively used benchmarks and pointed that 67.69% of the investigated networks presents a planar topology, while 21.85% shows a different number of transistors between its logic plans and 93.73% of the physical cells will contain at least one gap in its diffusion areas.

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