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Fully integrated chipset at E-band frequencies in a superhetrodyne architecture covering the lower 71-76GHz and upper 81-86GHz bands were designed and fabricated in 0.13µm SiGe technology. The receiver chips include an image-reject low-noise amplifier (LNA), RF-to-IF mixer, variable gain IF amplifier, quadrature IF-to-baseband de-modulators, tunable baseband filter, phase-locked loop (PLL), and frequency multiplier by four (quadrupler). The receiver chips achieve maximum gain of 65dB, 6dB noise figure, better than -10 dBm IIP3, with more than 65 dB dynamic range, and consumes 600 mW. The transmitter chips include a power amplifier, image-reject driver, IF-to-RF up-converting mixer, variable gain IF amplifier, quadrature baseband-to-IF modulator, PLL, and frequency quadrupler. It achieves output power at P 1dB of 17.5 to 18.5 dBm, P sat of 20.5 to 21.5 dBm, an analog controlled dynamic range of 30 dB and consumes 1.75 W.