A parallel, 12gm-pitch, low-power 6-b segmented digital-to-analog converter (DAC) array drives an array of 3gm x 3gm analog DRAM cells in a 2.5/1V 90 nm CMOS process, with an application in maskless lithography. An innovative self-calibrating compensation circuit limits the effect of charge leakage and capacitive process mismatch to less than 0.5LSB over lOOms of data hold time. A 2mm x 2mm test chip implements a mixed-signal interface with 32 DACs driving four 32 x 256 analog DRAM arrays.

While this book is called a &dquo;revised&dquo; edition, it is more than that. The majority of the cases are new and the text material represents a closer analytical survey of the subject. It is really a combination text and problem book. In comparison with the first edition it demonstrates:

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