Texas Instruments, Dallas, TXWireless communication applications demand A/D converters with wide signal bandwidths up to 4 MHz and 12b to 14b or better resolution. Compared to switched-capacitor (SC) implementations, continuous-time (CT) ∆Σ modulators have the advantages of lower power consumption for wideband operation, intrinsic anti-alias filtering, and better immunity to the high leakage problems inherent to deep submicron technologies. Prior CT ∆Σ modulators have relied on one amplifier per pole to realize higher-order noise shaping [1,3]. This can lead to a long design process, complex layout, and increased power and area. In addition, amplifiers can be difficult to scale from one CMOS process node to another.To reduce design complexity and area, several solutions have been tried in the past. One of these solutions realizes a 2 nd -order passive ∆Σ modulator with a 2-pole passive filter and a 1b quantizer [2]. In the present work, a high-DR, fourth-order, single-bit, CT, ∆Σ modulator is achieved by adding an active 2 nd -order loop on top of the PDSM loop described in [2]. A 4 th -order loop is implemented using just two-amplifiers plus passive components to realize the poles and zeros. This active-passive combination (APDSM) runs at a sampling rate of 256MHz with a peak SNR of 86dB for a 600kHz signal bandwidth.The implemented APDSM architecture, using one amplifier per loop, is shown in Fig. 27.3.1. The outer loop has 2-poles and 1zero, and the inner loop has 2-poles and 2-zeros realized with passive elements. The double loop is designed to minimize internal signal swings. The input to the 1 st amplifier (AMP1) is limited to ±15mV peak and its output is limited to less than ±100mV peak. The inputs to the 2 nd amplifier (AMP2) and to the comparator are limited to ±5mV peak. These small-signal swings reduce distortion and power consumption, simplify amplifier design, and allow low voltage (1.2V) operation.AMP1, which provides most of the loop gain, is realized by a lowvoltage, folded-cascode OTA as shown in Fig. 27.3.2. This amplifier has a large differential input pair with non-minimum channel lengths (for reduced offset and flicker noise); hence it also has a large transconductance gain that helps reduce the inputreferred noise. Any noise coupled inside the inner loop is reduced by the transconductance-resistance G m -R gain of AMP1. AMP2, shown in Fig. 27.3.3, serves to decouple the poles and zeros of the inner and outer loops. Thus, passive RC values can be easily determined from loop-gain, bandwidth, signal swing, and absolute A/D gain requirements. AMP2 is implemented using a simple differential pair with non-cascoded loads. The G m -R gain of AMP2 helps to further suppress the input-referred noise and offset of the comparator. The cascaded G m -R gain in the forward path allows the comparator to be implemented as a very small, high-speed, regenerative latch comparator without offset cancellation as in Fig. 27.3.4.The loop filter passive poles and zeros are implemented using NWELL resistors and, PMOS ...

A 40mA buck regulator operating in the inherently stable Discontinuous Conduction Mode (DCM) for the entire load range is presented. A Pulse Frequency Modulation (PFM) control scheme is implemented using a proposed Hysteretic-Assisted Adaptive Minimum-On-Time (HA-AMOT) controller to automatically adapt the regulator to a wide range of operating scenarios in terms of input, output, and passive component values while ensuring compensation-less DCM operation with minimized inductor peak current. Thus, compact silicon area, low quiescent current, high efficiency, and robust performance across all possible scenarios can be achieved without any calibration. Moreover, power-gating is employed in the analog circuits of the proposed controller to further improve efficiency at sub-1mA loads. The regulator is integrated within a low-power microcontroller in 90nm CMOS to power its digital core while allowing maximum flexibility in the powering options of the microcontroller and the choice of the passive components. It occupies 0.1mm 2 and achieves 92% peak efficiency, and 78.5% and 86% efficiency at 200µA and 40mA loads respectively. It handles an input in the range of 1.8V-4.2V, an output in the range of 0.9V-1.4V, an inductor in the range of 4.7µH-10µH, and an output capacitor in the range of 2.2µF-10µF without any calibration or re-optimization.

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