This paper describes a 155 MHz wide-word cache design and ifs test integration features. Design techniques f o r high speed CAM with single ended niarch line sensing and highly integruted RAM are described. A new cache BIST algorithm bused on the SMARCH [ I ] algorithm is presented. New techniques are described for the insertion of cache BIST access points into a high speed data path wifhoiit compromising mission mode performunce. Perfortnance results of cache tnetnory used for telecotntnunications microprocessor applications with 1Kb of CAM referencing a 5 Kb RAM are presented.

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