AbstiactThis paper presents the d e g m b o n of fT and f-in CMOS devices at elevated temperame. Since MOS transistors in RF applications are usually in d o n region and f7 of CMOS devices is proportional to g , a simple empirical model for temperature dependence of g, at any measurement bias has been suggested by considering the temperature dependence of a canier mobility and a saturation velocity simultaneously. From the empirical temperature behavior of g , we can predict the enhanced RF performances of CMOS at low temperatllre. in d o n region, the temperature dependence offT and f , should be characterized by the combination of the temperahlre dependence of pef and v , , . In this work, the temperature dependence of& and f , in CMOS devices have been measured. Since& and f , are proportional to g, the degradation of& and f , can be explained by a simple empirical model for tempemtm behavior of g, which was taken into considemtion of both canier mobility and d o n velocity degadahon. II . Device Fabrication and Measurement I . Introduction With the scaling towards an extreme sub-micrometer regime, a cut-off tkquency UT) of CMOS as high as 150 GHz and Si MMIC have been reported to replace GaAs MMIC in RF h n t e n d IC's[ 1-31. Generally, high channel tempeiature has well known detrimental effects on the performances of MOS devices such as threshold voltage shift, transconductance d e w o n , and distortion of the Dc I-V charactenstl cs. To explain the transconductance degradabon with the increase of temperature, there have been extensive studies on the temperature dependence of effective canier mobility ( p ) and saturation velocity (v, ), separately [4,5]. When the MOS transistor is operated in the saturation region, the channel region can be divided into two regions such as a strong inversion region and a velocity saturation region. Therefore, the tempemture dependent g behaviors in the saturation region should be described by the temperature dependence of p and v,, simultaneously. Particularly, since MOS transistors in RF applications are usually biased . . eff eliThe CMOS transistors used in this work were &-hid using a 0.8 wn twin-well CMOS process on the p Si with resistivity of 2000 Q an. The gate oxide thickness is 175A, and a TiSi silicide process was used to reduce the sowcedrain parasitic resistance. The gate pattern for RF chamcterization is multi-finger type with common sourcebulk configclration. All the test devices used in this work have 10 fingers with L4.8 rn and unit finger width Wu=lO lla Small signal scattering ( S ) m e t e r s have been measured using on-wafer RF probes of Cascade Microtech and a HP 8510C network analyzer at temperature ranging h m 300 to 473K.On-wafer dummy structures were employed to deembed pad parasites. Measured S parameters were converted into admittance (Y) parameters, and the inbinsic device characteristics were calculated in the Y domain by using a deembedded technology.The cut-off hquency V;) and maximum h u e n c y (&A have been determined as the frequency whe...
