A 1.2 micron O S chip set (processor and controller) has been designed for applications i n high performance FET based d i g i t a l signal processing systems. The processor chip performs about 500 million arithmetic o p r a t i o n s Fer second and operates a t an 1/0 r a t e of 5 billion b i t s per second. The controller chip provides t o t a l system control for FFT based DSP systems. Algorithm such a s FET, spectrum analysis, d i g i t a l f i l t e r i n g (via frequency domain) can be defined on the chip set by coding 5 t o 10 instructions i n t h e controller.Although a single chip set can process data rates a t very high speeds (e.g., lK FFT i n 61 ).IS), multiple stages can be cascaded very simply for extremely high performance (up t o 100 MHZ data rates).

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