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This paper proposes a specific low jitter and high speed Ouput interface which takes advantage of the Partially Depleted Silicon-on-Insulator technology while avoiding its drawbacks related to floating body effects. Thanks to an active body-biasing control technique, the additional jitter related to PD-SOI history effect, as well as the higher static leakage current compared to bulk technology, are more than compensated. In depth analyses are presented to highlight the robustness of this technique with respect to the other solutions considering various capacitive loads and temperatures.

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