Abstract-A measurement system for internal node testing of integrated circuits using a micromachined photoconductive sampling probe is described and characterized. Special emphasis is placed upon the system performance, demonstrating how absolute voltage measurements are achieved in a dc-to-mm-wave bandwidth. The feasibility of the setup is illustrated using an InP heterojunction bipolar transistor frequency divider. Detailed waveforms at different circuit nodes and the corresponding propagation delays from within this circuit at operating frequencies up to 10 GHz are presented. The results demonstrate for the first time the use of photoconductive probes for calibration-free, absolute-voltage, dc-coupled potential measurements in highfrequency and high-speed integrated circuits.

Several SEM inspection techniques for the process development of a 0.25 p.m T-gate MESFET process have been successfully utilized. The transition of these techniques to a manufacturing process with SPC monitoring will also be discussed. The unique challenges of imaging several different Ebeam resists, and their interaction with the scanning electron microscope will also be discussed. BACKGROUNDThe production of state of the art GaAs MESFET devices (which operate at 4-35+ GHz) requires low input capacitance devices with small gate resistances. One method of accomplishing these goals is the production of a T-gate. A T-gate is a gate that has a cross-section with a top larger than the bottom, or shaped like a "T". The small dimensions required for the bottom of the "T' are patterned by E-beam, and because of extremely tight registration requirements, the top of the "T" is also written by Ebeam.The combination of using 2 different Ebeam resists (with significantly different sensitivities) and a very precisely controlled dose and shape for the patterning electron beam, allows this "1"' feature to be patterned with only one exposure/develop sequence. Because the metal used in gate formation (Ti, Pt, and Au) are not readily etched, the actual metal gate structure is formed via a "lift-off" process. In a "lift-off' process the desired patterns are exposed and developed on the wafer (exposing bare GaAs) and then metal is evaporated over the entire wafer. After evaporation the remaining photoresist is dissolved away, leaving only the original exposed features on the wafer. Because the gate is formed via this metal "liftoff' process, both the size and the profile of the photoresist are critical to making the process reproducible. The following figures illustrate the exposure mechanism, and the idealized profile produced after development.The gate resulting after liftoff (and nitride passivation) is shown in Figure 2. 0-8194-1 160-4/93/$6.00 SPIE Vol. 1926 / 295 I EXPOSURE CAP EXPOSURE Figure 1. (a) Resist structure LOW SENSITIVITY RESIST 4-HIGH SENSITIVITY RESIST LOW SENSITIVITY RESIST (b) used for T-gate formation before exposure (a), and idealized profile after exposure(b) Downloaded From: http://proceedings.spiedigitallibrary.org/ on 06/24/2016 Terms of Use: http://spiedigitallibrary.org/ss/TermsOfUse.aspx

A micromachined photoconductive sampling probe is used to determine detailed wave forms at different circuit nodes and corresponding propagation delays from within an InP HBT frequency divider operating at 2.7 GHz. The results demonstrate for the first time the capability of photoconductive probes for absolutevoltage, DC-coupled potential measurements in integrated circuits.

No abstract