Abstract-Digital Phase locked loop (DPLL) is one of the most important devices in almost all the electronic systems. This paper introduces the design of DPLL using sub-micron 45nm CMOS technology and implemented using microwind 3.1 software. The Software microwind 3.1 is used to design and simulate an integrated circuit at physical description level. Two different frequencies are generated at different voltages and it is observed that as supply voltage reduces power consumption also reduces.