Multiplication is an arithmetic operation where we will perform some arithmetic operations on the input operands and obtains the final result. Natural multiplication involves partial products generation and adding the obtained partial products to get the final result. But it consumes more power and time if the bit-width increases. Hence, we will use a Dadda Multiplier which results in increasing the execution speed and power efficiency and we will observe the same on FPGA. Hence this arithmetic technique can be used in various error tolerant applications such as image processing, digital processing and FFT.

A digital comparator is a hardware electronic device or a combinational logic circuit. It is capable of comparing two numbers as input in binary form and determines the output. In the previous designs like in the design of XOR-XNOR(XE) with cross-coupled p-MOS, even though it occupies less area, the full swing output voltage can’t be able to produce which creates a problem when the bit width increases. To avoid this kind of disadvantages we are designing a N-bit digital comparator in a way such that it produces full swing output voltage with the improved power efficiency as well as the transistor count in the circuit also decreases. So that it can be used in several applications like scientific computations and test circuit applications etc.