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The Non‐Volatile Random Access Memory (NVRAM) is recently identified as the most upcoming main memory technology in Embedded and Internet of Things (IoT) systems due to its appealing qualities like zero static power consumption and great memory cell density. On the other hand, most NVRAMs have low write endurance due to workload‐induced write variance, leading to more write activity at a few blocks of memory than the other blocks. Improving the endurance of NVRAM on embedded architectures is very critical due to the limited constraints of Embedded architectures. The main goal of this paper is to address the complexity of NVRAM designs, with a focus on embedded boards, and to create a prototype that enhances NVRAM endurance using a compression technique. Furthermore, this framework is not particular to a single NVRAM device. An Instruction Per Cycle based Dynamic Pattern Compression (IPC_DPC) model is developed to address NVRAM's high write latency and low endurance. The primary goal of the proposed IPC_DPC model is to minimize the energy utilization and latency of heavy workloads during the execution by pre‐determining the workload's instruction cycles. The IPC_DPC model initially divides the Low IPC and High IPC workloads and then compresses the workloads dynamically based on their IPC values compared to the threshold factor. As a result, IPC_DPC improves the compression ratio and reduces the write latencies associated with traditional compressors, significantly reducing the write activity and improving the lifetime of NVRAM. We implemented the proposed IPC_DPC model using GEM5 with a Raspberry Pi board and took IoMT, MiBench, and EEMBC benchmarks for evaluation. Compared to FPC, BDI, FNW, and DFPC models, the proposed IPC_DPC model is shown to be more efficient in terms of compression ratio (56.05%) and energy reduction (17%).