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The paper contains the study results for processtolerant high-density layout design of hierarchical regular and irregular VLSI macroblocks. Process tolerance is ensured by the one-dimensional compaction algorithm based on the virtual grid, and high density by the original method of iterative stage-by-stage matching of cells and their pins location. The authors propose the structural model of complex irregular circuits' layout, which simplifies their cells matching. The description of the developed system and the technique of hierarchical layout design of complex microelectronic circuits are also presented.

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