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The post-silicon validation phase in a processor's design life cycle is geared towards finding all remaining bugs in the system. It is, in fact, our last opportunity to find functional and electrical bugs in the design before shipping it to customers.In this paper, we provide a high-level overview of the methodology and technologies put into use as part of the POWER8 post-silicon functional validation phase. We describe the results and list the primary factors that contributed to this highly successful bring-up.

Power ISA™ Version 3.1 has introduced a new family of matrix math instructions, collectively known as the Matrix-Multiply Assist (MMA) facility. The instructions in this facility implement numerical linear algebra operations on small matrices and are meant to accelerate computation-intensive kernels, such as matrix multiplication, convolution and discrete Fourier transform. These instructions have led to a power-and area-efficient implementation of a high throughput math engine in the future POWER10 processor. Performance per core is 4 times better, at constant frequency, than the previous generation POWER9 processor. We also advocate the use of compiler builtins as the preferred way of leveraging these instructions, which we illustrate through case studies covering matrix multiplication and convolution.