Approximate computing can be used in the error-tolerant applications since it can provide meaningful results with lower power consumption. In this study, the authors proposed a novel imprecise 4-2 compressor which is used in the multipliers of image processing applications. Besides the output values, they also consider the pattern distribution to resynthesise the 4-2 compressor in imprecise style. Compared to the precise compressor, the proposed imprecise 4-2 compressor can reduce power consumption and delay by 56 and 39%. Compared to the precise multiplier, the simulation results show that the multiplier which uses the proposed imprecise 4-2 compressor can achieve 33 and 30% improvement in power consumption and delay, respectively. In addition, the image quality of their design is good for human perception because peak signal-to-noise ratio PSNR values are more than 33 and mean structural similarity values are more than 0.99. Even compared to the related imprecise works, their design has a better error rate to improve the quality of images while maintains both the high power efficiency and low circuit complexity.

The radix-4 Booth algorithm is widely used to improve the performance of multiplier because it can reduce the number of partial products by half. However, numerous additional encoders and decoders would cause the power consumption of the Booth multiplier to be considerable. In this paper, a new radix-4 Booth pre-encoded mechanism is proposed to reduce the power consumption of the Booth multiplier. The proposed design can effectively reduce the power of the Booth multiplier dissipated in the redundant activities by disabling the Booth encoders and decoders from unnecessary working. Particularly, since the control signals are generated early at the pipeline input register before the multiplier, the performance of our design is better than the traditional Booth multiplier. Based on the TSMC 40 nm technology, the simulation results show that the proposed pre-encoded mechanism can reduce the dynamic and static power by 45% and 65%, respectively, compared to the traditional 16-bit radix-4 Booth multiplier. Compared to the previous designs, the proposed design keeps the feature of race-free and has lower power consumption. Even compared to the approximate design, the proposed design has better power efficiency and can provide the exact products.

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