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A power-optimized 8-bit priority encoder cell that simplifies the conventional circuit from 102 to 62 transistors is presented. A parallel priority look-ahead architecture that reduces the delay time of priority propagation is introduced. The 8-bit PE cell and parallel priority look-ahead architecture are applied to the design of a 64-bit PE in a latch-based two-stage pipelined structure. Simulation results shows that the 64-bit PE is 27% faster and 53% more power efficient than the conventional design using the same process technology.

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