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A floorplanning algorithm for novel carbon nanotube based three-dimensional integrated circuits is proposed. It is based on ant colony algorithm. The proposed algorithm can optimize the area and area-delay for the single device layer in the three-dimensional integrated circuits, and then optimize the whole 3D IC's area and delay. After the optimization, the performance can improve about 15%.

Based on the software ISE and EDK, a verification system of USB2.0 IP core which is designed in the authors' lab for System-on-a-Chip (SoC) application is proposed. The top-level design is in the ISE and an embedded sub-module is included in the ISE top project. The C code for operating the IP core is also done. All the work is downloaded to FPGA board, so the correctness of the IP core is verified.978-1-4244-4888-3/09/$25.00 ©2009 IEEE