<em><span>This paper proposes performance based macro modeling of analog circuit using Multi Output Modeling (MOM) with the help of Support Vector Machine (SVM). SVM models the analog circuits and provides a relation between multi-input and multi-output parameters. In this work, Voltage Controlled Oscillator (VCO) is modeled as a test circuit which is designed in Cadence Virtuoso GPDK 45nm technology. From the Spice simulation results, the feasible dataset has been extracted from the complete dataset. Then, the VCO output frequency and phase noise is modeled by the width of the transistors which are the input parameters of the transistors. After tuning the model properly by k-cross validation method, the accuracy was found to be 96.1% which is good enough to make it use for the circuit synthesis purpose.</span></em>

<em>In this paper floating gate MOS (FGMOS) along with sleep transistor technique and leakage control transistor (LECTOR) technique has been used to design low power SRAM cell. Detailed investigation on operation, analysis and result comparison of conventional 6T, FGSRAM, FGSLEEPY, FGLECTOR and FGSLEEPY LECTOR has been done. All the simulations are done in Cadence Virtuoso environment on 45 nm standard CMOS technology with 1 V power supply voltage. Simulation results show that FGSLEEPY LECTOR SRAM cell consumes very low power and achieves high stability compared to conventional FGSRAM Cell</em>