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Abstract--The coming of multimedia era and information security era indicates that must process longer digit integer data. Previous sort researches focus on pure performance of large amount of finite fixed digit/bit number. This paper discusses on effectively solving arbitrary long digit integer sorting problem by HW/SW co-design under the Area×Time 2 (AT 2 ) price-performance constraint. The work proposes multi-level (two-level) sort architecture to attain the object: an accomplished fixed-digit (k-bit) hardware sorter implements the first or basic level sorting, software programmed radix 2 k sort implements the second or higher level sorting. By Super Radix Sorting HW/SW co-design and reuse techniques, the work makes fixed-digit HW sorters more flexible and useful.

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This investigation concerns the improvement of protection and comfort for long-range airliner passengers. The study proposes an airtight box design concept, which has few of the potential discomforts associated with the conventional airliner environment. It provides real privacy, quiet, a comfortable humidity level, personalized air conditioning, positive/negative pressure isolation, and more safety promises. The proposed design redefines 'safety' and 'amenity' for the first-class and business-class cabins of long-range airliners. In the post-SARS age, it should effectively increase the loyalty of passengers and the profit of the airline. Index Term-Boeing 7E7, BWB, Airbus A380, long-range airliner, SARS, Bio-Safety Level and damage control.

The comparator is a very basic and useful arithmetic component of digital systems. An individual, compact, high-performance, good cost-benefit ratio comparator core plays an important role on almost all hardware sorters. The study proposes a tine cost-performance ratio comparator design. Based on modified 1's complement principle and conditional sum adder scheme, the proposed design has small transistor count and short propagation delay. Post-layout simulations based on TSMC 0.6um lP3M CMOS process has completed. It shown a 64-b static CMOS comparator of the proposed architecture only needs 1,556 transistors and 4.211s.